The present invention is generally directed to a system and method for selective application and reconciliation of hierarchical sets of circuit design constraints within a circuit design editor.
More particularly, the subject system and method relate to user-friendly and largely automated management, modification, and selective application of circuit design constraints towards a more efficient reconciliation thereof in designing and fabricating an integrated circuit (IC) product.
Presently, a circuit design may incorporate upwards of tens of billions of transistors or more and the number of transistors is expected to continue doubling every eighteen months. To conservatively estimate circuit performance and avoid emergent problems with fabricated circuit products, a number of conservative and pessimistic constraints are applied to various hierarchical regions of a circuit design. In such manner, a host of constraints may apply to a circuit design, specific layers thereof, specific types of fabrication/foundry technology, specific bounded portions, nets, specific objects, and the like. A substantial number of overly-pessimistic constraints may apply to each object in a circuit design to ensure the fabricated product functions appropriately in all operational environments. A single object may be constrained globally via the host of constraints illustrated above including: an application or foundry set of constraints, design constraints, net constraints, group constraints, bounded area constraints, constraints related to the specific circuit object, and the like.
When a circuit designer utilizes an electronic design automation (EDA) tool such as a circuit layout editor, schematic editor, or the like, each editing interaction (such as, for example, adding, modifying, moving, or removing one or more circuit objects) may result in a number of violations of the hierarchical circuit design constraints. Determining which of the plural sets of constraints which may apply to the editing interaction or the modified circuit object (or its neighbors) has heretofore been a challenge. No suitable constraint editor for expeditious constraint determination and reconciliation while maintaining context within an EDA tool has heretofore been available.
Previous products in the art have required the user to depart from the circuit editing EDA tool and manually traverse the sets of constraints applicable to the circuit design to locate the specific constraint(s), constrained value(s), and parameter(s) or object(s) modified in the editing interaction likely to violate one of the sets of constraints. Once located, the circuit designer was required to modify/reconcile the constraints/objects in an intelligent manner while effectively blind to the context of the violation within the circuit design. Such systems heretofore known deprived the circuit designer of the contextual relation between circuit objects, editing interaction, constraints, and other related objects.
Such deficiencies have heretofore hindered efforts to minimize fabricated integrated circuit product cost, time-to-market, power requirements, and substrate area, while maximizing performance.
There is therefore a need for a system and method for selective application and reconciliation of hierarchical ordered sets of circuit design constraints within a circuit design editor.